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K7K3218T2C - 1Mx36 & 2Mx18 DDRII CIO b2 SRAM

Description

Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Contro

Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future freguency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V.
  • Pipelined, double-data rate operation.
  • Common data input/output bus.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Read latency : 2 clock cycles.
  • Registered address, control and data input/o.

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Datasheet Details

Part number K7K3218T2C
Manufacturer Samsung Semiconductor
File Size 440.01 KB
Description 1Mx36 & 2Mx18 DDRII CIO b2 SRAM
Datasheet download datasheet K7K3218T2C Datasheet
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K7K3236T2C K7K3218T2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 36Mb DDRII+ SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.
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