K7K3236U2C
K7K3236U2C is 1Mx36 & 2Mx18 DDRII CIO b2 SRAM manufactured by Samsung Semiconductor.
- Part of the K7K3218U2C comparator family.
- Part of the K7K3218U2C comparator family.
FEATURES
- 1.8V+0.1V/-0.1V Power Supply.
- DLL circuitry for wide output data valid window and future freguency scaling.
- I/O Supply Voltage 1.5V+0.1V/-0.1V
- Pipelined, double-data rate operation.
- mon data input/output bus .
- HSTL I/O
- Full data coherency, providing most current data.
- Synchronous pipeline read with self timed late write.
- Read latency : 2.5 clock cycles
- Registered address, control and data input/output.
- DDR(Double Data Rate) Interface on read and write ports.
- Fixed 2-bit burst for both read and write operation.
- Clock-stop supports to reduce current.
- Two input clocks(K and K) for accurate DDR timing at clock rising edges only.
- Two echo clocks (CQ and CQ) to enhance output data traceability.
- Data Valid pin(QVLD) supported
- Single address bus.
- Byte write (x18, x36) function.
- Simple depth expansion with no data contention.
- Programmable output impedance(ZQ).
- JTAG 1149.1 patible test access port.
- 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm Organization Part Number K7K3236U2C-F(E)C(I)45 X36 K7K3236U2C-F(E)C(I)40 K7K3236U2C-F(E)C(I)33 K7K3218U2C-F(E)C(I)45 X18 K7K3218U2C-F(E)C(I)40 K7K3218U2C-F(E)C(I)33 Cycle Access Unit Time Time 2.22 2.5 3.0 2.22 2.5 3.0 0.45 0.45 0.45 0.45 0.45 0.45 ns ns ns ns ns ns
- -F(E)C(I) F(E) [Package type] : E-Pb Free, F-Pb C(I) [Operating Temperature] : C-mercial, I-Industrial
FUNCTIONAL BLOCK DIAGRAM
36 (or 18) DATA REG
36 (or 18) 19 (or 20) WRITE/READ DECODE WRITE DRIVER 72 (or 36) SENSE AMPS 1Mx36 (2Mx18)...
