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LC322271M - 2 MEG (131072 words X 16 bits) DRAM

This page provides the datasheet information for the LC322271M, a member of the LC3 2 MEG (131072 words X 16 bits) DRAM family.

Datasheet Summary

Features

  • 131072 words × 16 bits configuration. Single 5 V ± 10% power supply. All input and output (I/O) TTL compatible. Supports fast page mode, read-modify-write and byte write. Supports output buffer control using early write and Output Enable (OE) control. 8 ms refresh using 512 refresh cycles. Supports RAS-only refresh, CAS-before-RAS refresh and hidden refresh. Follows the JEDEC 1 M DRAM (65536 words × 16 bits.

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Datasheet preview – LC322271M

Datasheet Details

Part number LC322271M
Manufacturer Sanyo
File Size 1.12 MB
Description 2 MEG (131072 words X 16 bits) DRAM
Datasheet download datasheet LC322271M Datasheet
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Full PDF Text Transcription

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Ordering number : EN*5085A CMOS LSI LC322271J, M, T-70/80 2 MEG (131072 words × 16 bits) DRAM Fast Page Mode, Byte Write Preliminary Overview The LC322271J, M and T is a CMOS dynamic RAM operating on a single 5 V power source and having a 131072 words × 16 bits configuration. Equipped with large capacity capabilities, high speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment. Address input utilizes a multiplexed address bus which permits it to be enclosed in a compact plastic package of SOJ 40-pin, SOP 40-pin, and TSOP 44-pin .
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