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SLX24C64 - 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs/ I2C Synchronous 2-Wire Bus

Description

Serial Clock (SCL) The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.

Features

  • Data EEPROM internally organized as 1024/2048 bytes and 64/128 pages × 16 bytes.
  • Low power CMOS.
  • VCC = 2.7 to 5.5 V operation.
  • Two wire serial interface bus, I2C-Bus compatible.
  • Filtered inputs for noise suppression with Schmitt trigger.
  • Clock frequency up to 400 kHz.
  • High programming flexibility.
  • Internal programming voltage.
  • Self timed programming cycle including erase.
  • Byte-write and page-write programm.

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Other Datasheets by Siemens Semiconductor Group
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Full PDF Text Transcription

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Standard EEPROM ICs SLx 24C08/16 8/16 Kbit (1024/2048 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus Data Sheet 1998-07-27 SLx 24C08/16 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 3 5 4, 5 5 11, 12 15 19 20 20 20 I2C Bus Current Version: 1998-07-27 06.97 Subjects (major changes since last revision) 3 5 4, 5 – 11, 12 15 19 20 20 20 Text was changed to “Typical programming time 5 ms for up to 16 bytes”. WP = VCC protects upper half entire memory. CS0, CS1 and CS2 were replaced by n.c. The paragraph “Chip Select (CS0, CS1, CS2)” was removed completely. The erase/write cycle is finished latest after 10 8 ms. Figure 11: second command byte is a CSR and not CSW. “Capacitive load …” were added. Some timings were changed.
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