SDA9253 Datasheet | Siemens Semiconductor Group

Features q q q q q q q q q q q q q q q q q CMOS IC 212 × 64 × 16 × 12-bit organization Triple port architecture One 16 × 12-bit input shift register Two 16 × 12-bit output shift registers Shift registers independently and simultaneously accessible Continuous data flow even at maximum speed 40-MHz shift rate - 0.96-Gbit/s total data rate All inputs and outputs TTL-patible Tristate outputs Random access of groups of 16 × 12 bits for a wide range of applications Refresh-free operation possible 5 V ± 10 % power supply 0 … 70 °C operating temperature range Low power dissipation: 700 m W active, 28 m W standby Suitable for all mon TV standards Allows flicker and noise reduction simultaneously with only one field memory Applications: TV, VCR, image processing, video printers, data pressors, delay lines, time base correctors, HDTV P-MQFP-64-1 Type SDA 9253 Ordering Code Q67101-H5171 Package P-MQFP-64-1 Semiconductor Group 1998-01-30 SDA 9253 Functional Description The SDA 9253 is a triple port 2605056 bit dynamic sequential-access memory for high-data-rate video applications. It is organized as 212 rows by 64 columns by 16 arrays by 12 bit to allow for the storage of 12-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality (13.5-MHz basic sample rate) or 12-bit planes of parts of a HDTV field. The memory is fabricated using the same CMOS technology used for 4-Mbit standard dynamic random access memories. The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit length and 12-bit width, which perform a serial to parallel conversion between the asynchronous input/output data streams and the memory array. The parallel data transfer from the 16 × 12-bit input shift register C to an addressed location of the memory array and from the memory array to one of the 16 × 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column address (SAC) which contains the desired column...