SDA9254-2 Datasheet | Siemens Semiconductor Group

Features q q q q q q q q q SDA 9254-2 CMOS IC q q q q q q q q q q q q Stores a plete video field (4:1:1) On chip adaptive recursive noise reduction filter (4:1:1) 4 noise reduction classes selectable Special noise reduction mode for 4:2:2 applications 212 × 64 × 16 × 12-bit organization Triple port architecture One 16 × 12-bit input shift register Two 16 × 12-bit output shift registers Shift registers independently and simultaneously accessible (one output shift register is used internally for noise reduction filtering) Continuous data flow even at maximum speed 40-MHz shift rate - 0.96-Gbit/s total data rate All inputs and outputs TTL-patible Tristate outputs Random access of groups of 16 × 12 bits for a wide range of applications Refresh-free operation possible 5 V ± 10 % power supply 0 … 70 °C operating temperature range Low power dissipation: 700 m W active, 28 m W standby Suitable for all mon TV standards Allows flicker and noise reduction simultaneously with only one field memory Applications: TV, VCR, image processing, video printers, data pressors, delay lines, time base correctors, HDTV P-MQFP-64-1 Type SDA 9254-2 Ordering Code on request Package P-MQFP-64-1 Semiconductor Group 1998-01-16 SDA 9254-2 Functional Description General The SDA 9254-2 is a bination of the TV-SAM SDA 9253 and an adaptive recursive filter to achieve a reduction of noise for video signals. To get a closed loop one of the two output ports of the triple port memory is connected internally to the noise reduction filter. External access to this port is not possible. The characteristic of the noise reduction filter is adjustable via three pins (CLASS2, CLASS1, CLASS0). SDC0 ... 11 BLN NR422 CLASS 12 Noise Reduction Filter 3 Port C Field Memory Port B Port A SQA0 ... 11 UEB10379 Figure 1 Block Diagram The memory capacity of the SDA 9254-2 enables a field based filtering of 4:1:1 video signals (pin NR422 = ‘0’). 4:2:2 applications are supported by a special...