SDA9257 Datasheet | Siemens Semiconductor Group

Features q q q q MOS IC q q q q q q All settings made by I2C Bus PLL lock-in behavior can be set to TV- or VCR mode Automatic clamping of CVBS input Provides all horizontal and vertical sync signals and clocks for operating PAMUX, analog color decoders, the A/D converters, PSND and Featurebox Free-running capability Frequency generator function possible with digitally P-DIP-28-1 adjustable frequency Lock-in function of the PLL on CVBS also possible with externally supplied 24-MHz or 27-MHz clock Multi-standard operation (50 Hz, 60 Hz; PAL, NTSC, SECAM) Vertical noise suppression and 50/60-Hz detection Serial digital output for actual frequency value and CVBS-black level Applications q q q q Memory based image improvement with analog color decoder Memory based image improvement with digital multi-standard decoder Free-running sync generator Digital frequency synthesizer Type SDA 9257 Functional Description Ordering Code Q67100-H5038 Package P-DIP-28-1 The clock sync generator consists essentially of the following function blocks (refer to block diagram): Analog clamping 7-bit, 27-MHz A/D converter Sync processor with digital horizontal PLL, vertical sync processor and pulse generator Clock generator with discrete timing oscillator, D/A converter, analog PLL and divider, as well as a crystal oscillator q I2C Bus interface q Button flutter elimination q q q q Semiconductor Group SDA 9257 Circuit Description 1 Horizontal PLL (HPLL) The CVBS is clamped before A/D conversion such that the H-sync pulse level is applied to the analog ground. Conversion takes place with 7 bits and a nominal frequency of 27 MHz. The digital HPLL filters the signal with a cutoff frequency of 1 MHz for a decimated clock frequency of 13.5 MHz, then measures the black level, calculates the sync threshold and determines the phase difference between the horizontal pulse and its own phase position. By means of digital PI filtering an increment is gained from this for the...