82S16
DESCRIPTION
The 82S16 and 82S17 are Schottky clamped TTL, read/ write memory arrays organized as 256 words of one bit each. They feature either open collector or tri-state output options for optimization of word expansion in bussed organizations. Memory expansion is further enhanced by full on-chip address decoding, 3 chip enable inputs and PNP input transistors which reduce input loading to 25p A for a "1" level, and -250p A (S82S16/17) or -100p A (N82S16/17) for a "0" level.
During WRITE operation, the logical state of the output of both devices follows the plement of the data input being written. This feature allows faster execution of WRITE-READ cycles, enhancing the performance of systems utilizing indirect addressing modes, and/or requiring immediate verification following a WRITE cycle.
Both devices have fast read access and write cycle times, and thus are ideally suited in high-speed memory applications such as "Cache", buffers, scratch pads, writable control stores, etc.
Both...
