SiS5571 Overview
System Block Diagram PBSRAM SiS5571 Pentium PCI/ISA Chipset CPU Master IDE Keyboard USB Tag RAM Host Address Host Data Bus MD Bus SiS5571 MA Bus DRAM ISA Device ISA Bus ISA Device ISA Device ISA Device PCI Bus PCI Device PCI Device PCI Device PCI Device Preliminary V21.00 July 18December 9, 1996 1 Systems Corporation Silicon Integrated SiS5571 Pentium PCI/ISA Chipset.
SiS5571 Key Features
- Supports Intel Pentium CPU and other patible CPU at 75/66/60/50MHz
- Supports the Pipelined Address Mode of Pentium CPU
- Supports the Full 64-bit Pentium Processor data Bus
- Supports 32-bit PCI Interface
- Integrated Second Level ( L2 ) Cache Controller
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 16K bits Dirty Ram
- Supports Pipelined Burst SRAM
- Supports 256 KBytes to 512 MBytes Cache Sizes