SI5376 Datasheet | Silicon Labs

Features - Highly-integrated, 4 PLL clock - Supports all ITU G.709 and any multiplier/jitter attenuator custom FEC ratios (239/237, - Four independent DSPLLs support 255/238, 255/237, 255/236, 253/226) any-frequency synthesis and jitter - Integrated loop filter with attenuation programmable bandwidth - 8 inputs/8 outputs - Simultaneous free-run and - Each DSPLL can generate any synchronous operation frequency from 2 k Hz to 808 MHz - Automatic/manual hitless input clock from a 2 k Hz to 710 MHz input switching - 350 fs rms (12 k Hz- 20 MHz) and - Selectable output clock signal format 410 fs rms (50 k Hz- 80 MHz) (LVPECL, LVDS, CML, CMOS) typical - LOL and interrupt alarm outputs - Meets ITU-T G.8251 and Telcordia - I2C programmable GR-253-CORE OC-192 jitter specifications - Single 1.8 V ±5% or 2.5 V ±10% operation with high PSRR on-chip - Programmable loop bandwidth: voltage regulator 60 Hz to 8 k Hz - 10x10 mm PBGA - Faster lock acquisition pared to the Si5374: <1.2 s - For a very low-loop BW version, see the Si5374 Applications - High-density, any-port, any-protocol, - 1/2/4/8/10G Fibre Channel any-frequency line cards - Gb E/10 Gb E Synchronous Ethernet - ITU-T G.709 OTN custom FEC - Carrier Ethernet, multi-service - 10/40/100G switches and routers - OC-48/192, STM-16/64 - MSPP, ROADM, P-OTS, muxponders Description The Si5376 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub-1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts two input clocks ranging from 2 k Hz to 710 MHz and generates two independent synchronous output clocks ranging from 2 k Hz to 808 MHz. The device provides virtually any frequency translation bination across this operating range. For asynchronous, free-running clock generation applications, the Si5376’s reference oscillator can be used as a clock source for any of the four DSPLLs. The Si5376 input clock frequency and clock...