SI5376 Description
The Si5376 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub-1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts two input clocks ranging from 2 kHz to 710 MHz and generates two independent synchronous output clocks ranging from 2 kHz to 808 MHz. The device provides virtually any frequency translation bination across this operating...
SI5376 Key Features
- Highly-integrated, 4 PLL clock
- Supports all ITU G.709 and any
- Four independent DSPLLs support
- 8 inputs/8 outputs
- Simultaneous free-run and
- Each DSPLL can generate any
- Automatic/manual hitless input clock
- 350 fs rms (12 kHz- 20 MHz) and
- Selectable output clock signal format
- LOL and interrupt alarm outputs