SL23EP09
Overview
The SL23EP09 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin.
- 10 to 220 MHz operating frequency range
- Low output clock skew: 45ps-typ
- Low output clock jitter: 50 ps-typ cycle-to-cycle jitter 20 ps-typ period jitter
- Low part-to-part output skew: 90 ps-typ
- Wide 2.5 V to 3.3 V power supply range
- Low power dissipation: 26 mA-max at 66 MHz and VDD=3.3 V 24 mA-max at 66 MHz and VDD=2.5V
- One input drives 9 outputs organized as 4+4+1
- Select mode to bypass PLL or tri-state outputs
- SpreadThru™ PLL that allows use of SSCG
- Standard and High-Drive options
