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Si5317
PIN-CONTROLLED 1–711 MHZ JITTER CLEANING CLOCK
Features
Provides jitter attenuation for any clock Selectable output clock signal
frequency
format: LVPECL, LVDS, CML or
One clock input / two clock outputs
CMOS
Input/output frequency range:
Single supply: 1.8, 2.5, or 3.3 V
1–711 MHz
Loss of lock and loss of signal
Ultra low jitter: 300 fs
alarms
(12 kHz–20 MHz) typical
VCO freeze during LOS/LOL
Simple pin control interface
On-chip voltage regulator with high
Selectable loop bandwidth for jitter
PSRR
attenuation: 60 Hz–8.