Si5319 Datasheet | Silicon Labs

Features - Generates any frequency from 2 k Hz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 k Hz to 710 MHz - Ultra-low jitter clock output with jitter generation as low as 0.3 ps rms (50 k Hz- 80 MHz) - Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 k Hz) - Meets OC-192 GR-253-CORE jitter specifications - Clock or crystal input with manual clock selection - Selectable clock output signal format (LVPECL, LVDS, CML, CMOS) - Support for ITU G.709 and custom OTN FEC ratios (e.g. 255/238, 255/237, 255/236) - Supports various frequency translations for Synchronous Ethernet - LOL, LOS alarm outputs - I2C or SPI programmable - On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10% or 3.3 V ±10% operation - Small size: 6 x 6 mm 36-lead QFN - Pb-free, ROHS pliant Applications - 10G/40G/100G OTN line cards - SONET/SDH OC-48/STM-16 and...