Si53204 Datasheet | Silicon Labs

FEATURES - 12/8/4-output 100 MHz PCIe Gen1/2/3/4/5pliant clock fanout buffer - Low additive jitter: 0.02 ps rms max, Gen 5 - Low-power, push-pull, HCSL patible differential outputs - 10 MHz to 200 MHz clock input - Individual hardware control pins and I2C controls for Output Enable - Spread spectrum tolerant to pass through a spread input clock for EMI reduction - Supports Intel QPI/UPI standards - Single 1.5 to 1.8 V power supply - Internal 100 Ω or 85 Ω output impedance matching - Adjustable output slew rate - Temperature range: - 40 °C to 85 °C - Package options: - 64-pin QFN (9 x 9 mm) : 12-output - 48-pin QFN (6 x 6 mm) : 8-output - 32-pin QFN (5 x 5 mm) : 4-output - Small QFN packages - Pb-free, Ro HS-6 pliant silabs. | Building a more connected world. Rev. 1.0 1. Feature List Si53212/Si53208/Si53204 Data Sheet Feature List - 12/8/4-output 100 MHz PCIe Gen1/2/3/4/5 and SRIS pliant clock fanout buffer - Low-power, push-pull, HCSL patible differential outputs from 10 MHz to 200 MHz clock input - Low additive jitter of 0.02 ps rms max to meet PCIe Gen 5 specifications - Individual hardware control pins and I2C for Output Enable to easily disable unused outputs for power savings - Spread spectrum tolerant to pass through a spread input clock for EMI reduction - Supports Intel QPI/UPI jitter requirements with margin - Internal 100 Ω or 85 Ω output impedance matching - Eliminates external termination resistors to reduce board space - Adjustable slew rate to improve signal quality for different applications and board designs - Single 1.5- 1.8 V power supply - Temperature range: - 40°C to 85°C - Package options: - 64-pin QFN (9 x 9 mm), 12-output - 48-pin QFN (6 x 6 mm),...