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Si53204 - Low Power Gen 1/2/3/4/5 Clock Buffer

This page provides the datasheet information for the Si53204, a member of the Si53212 Low Power Gen 1/2/3/4/5 Clock Buffer family.

Product Overview

Silicon Laboratories

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Si53204 Low Power Gen 1/2/3/4/5 Clock Buffer by Silicon Laboratories - Datasheet Preview — Datasheet preview – Si53204

Datasheet Details

Part number	Si53204
Manufacturer	Silicon Laboratories
File Size	868.87 KB
Description	Low Power Gen 1/2/3/4/5 Clock Buffer
Datasheet	Si53204 Datasheet
Additional preview pages of the Si53204 datasheet.

Si53204 Product details

Features

12/8/4-output 100 MHz PCIe Gen1/2/3/4/5compliant clock fanout buffer.
Low additive jitter: 0.02 ps rms max, Gen 5.
Low-power, push-pull, HCSL compatible differential outputs.
10 MHz to 200 MHz clock input.
Individual hardware control pins and I2C controls for Output Enable.
Spread spectrum tolerant to pass through a spread input clock for EMI reduction.
Supports Intel QPI/UPI standards.
Single 1.5 to 1.8 V power supply.

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Other Datasheets by Silicon Laboratories

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Published: Apr 12, 2019 |