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Si53208 Datasheet

Low Power Gen 1/2/3/4/5 Clock Buffer

Manufacturer: Silicon Laboratories

This datasheet includes multiple variants, all published together in a single manufacturer document.

Si53208 Overview

All differential clock outputs are pliant to PCIe Gen1/2/3/4/5 mon clock and separate reference clock specifications. This family of buffers is spread spectrum tolerant to pass through a spread input clock. Each device has an individual hardware output enable control pin for enabling and disabling each differential output.

Si53208 Key Features

  • 12/8/4-output 100 MHz PCIe Gen1/2/3/4/5pliant clock fanout buffer
  • Low additive jitter: 0.02 ps rms max, Gen 5
  • Low-power, push-pull, HCSL patible
  • 10 MHz to 200 MHz clock input
  • Individual hardware control pins and I2C
  • Spread spectrum tolerant to pass through
  • Supports Intel QPI/UPI standards
  • Single 1.5 to 1.8 V power supply
  • Internal 100 Ω or 85 Ω output impedance
  • Adjustable output slew rate

Si53208 Distributor