SST34HF3243B
SST34HF3243B is 32M-bit Concurrent SuperFlash + SRAM Combo Memory manufactured by Silicon Storage Technology.
- Part of the SST34HF3223B comparator family.
- Part of the SST34HF3223B comparator family.
FEATURES
:
- Flash Organization: Two 1M x16
- Quad-Bank Architecture for Concurrent Read-While-Write Operation
- 12 Mbit + 4 Mbit + 12 Mbit + 4 Mbit
- SRAM Organization:
- 2 Mbit: 256K x8 or 128K x16
- 4 Mbit: 512K x8 or 256K x16
- Single 2.7-3.3V Read-While-Write Operations
- Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
- Low Power Consumption:
- Active Current: 35 m A (typical)
- Standby Current: 25 µA (typical)
- Sector-Erase Capability
- Uniform 1 KWord sectors
- Block-Erase Capability
- Uniform 32 KWord blocks
- Read Access Time
- Flash: 70 and 90 ns
- SRAM: 70 and 90 ns
- Latched Address and Data
- Fast Erase and Word-Program:
- Sector-Erase Time: 18 ms (typical)
- Block-Erase Time: 18 ms (typical)
- Chip-Erase Time: 70 ms (typical)
- Word-Program Time: 14 µs (typical)
- Chip Rewrite Time: 30 seconds (typical)
- Automatic Write Timing
- Internal VPP Generation
- End-of-Write Detection
- Toggle Bit
- Data# Polling
- CMOS I/O patibility
- JEDEC Standard mand Set
- Packages Available
- 56-ball LFBGA (10mm x 12mm x 1.4mm)
PRODUCT DESCRIPTION
The SST34HF3223B/3243B bo Memory devices integrate four CMOS flash memory banks with a 256K x8 / 128K x16 or 512K x8 / 256K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP). These devices are fabricated using SST’s proprietary, high-performance CMOS Super Flash technology incorporating the split-gate cell design and thick oxide tunneling injector to attain better reliability and manufacturability pared with alternate approaches. The SST34HF3223B/3243B devices are ideal for applications such as cellular phones, PDAs and other portable electronic devices in a low power and small form factor system. The SST34HF3223B/3243B features multiple flash memory bank architecture allowing for concurrent operations between the four flash memory banks and the SRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The...
