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CXL5003P - CMOS-CCD 1H Delay Line for PAL

Datasheet Summary

Description

The CXL5003M/P are general-purpose CMOS-CCD delay line ICs that provide 1H delay time for PAL.

Features

  • Low power consumption 110mW (Typ. ).
  • Small size package (8-pin SOP, DIP).
  • Low differential gain DG = 3% (Typ. ).
  • Input signal amplitude 180 IRE (= 1.28Vp-p, Max. ).
  • Low input clock amplitude operation 150mVp-p (Min. ).
  • Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits) Functions.
  • 848-bit CCD register.
  • Clock drivers.
  • Autobias circuit.
  • Sync tip clamp circuit.
  • Sa.

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Datasheet preview – CXL5003P

Datasheet Details

Part number CXL5003P
Manufacturer Sony Corporation
File Size 98.19 KB
Description CMOS-CCD 1H Delay Line for PAL
Datasheet download datasheet CXL5003P Datasheet
Additional preview pages of the CXL5003P datasheet.

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Full PDF Text Transcription

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CXL5003M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5003M/P are general-purpose CMOS-CCD delay line ICs that provide 1H delay time for PAL. Features • Low power consumption 110mW (Typ.) • Small size package (8-pin SOP, DIP) • Low differential gain DG = 3% (Typ.) • Input signal amplitude 180 IRE (= 1.28Vp-p, Max.) • Low input clock amplitude operation 150mVp-p (Min.
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