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CXL5005P - CMOS-CCD 1H Delay Line for NTSC with PLL

Datasheet Summary

Description

The CXL5005M/P are general-purpose CCD delay line ICs which provide 1H delay time of NTSC.

Features

  • Low power consumption 90mW (Typ. ).
  • Small size package (14-pin SOP, DIP).
  • Low differential gain DG = 3% (Typ. ).
  • Input signal ampiitude 180 IRE (= 1.28Vp-p, max. ).
  • Low input clock amplitude operation 200mVp-p (Min. ).
  • Built-in triple PLL circuit.
  • Built-in peripheral circuits (clock driver, timing generator, auto-bias and output circuits) Functions.
  • 680-bit CCD register.
  • Clock drivers.
  • Autobias circuit.

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Datasheet preview – CXL5005P

Datasheet Details

Part number CXL5005P
Manufacturer Sony Corporation
File Size 112.28 KB
Description CMOS-CCD 1H Delay Line for NTSC with PLL
Datasheet download datasheet CXL5005P Datasheet
Additional preview pages of the CXL5005P datasheet.

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Full PDF Text Transcription

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CXL5005M/P CMOS-CCD 1H Delay Line for NTSC with PLL Description The CXL5005M/P are general-purpose CCD delay line ICs which provide 1H delay time of NTSC. Features • Low power consumption 90mW (Typ.) • Small size package (14-pin SOP, DIP) • Low differential gain DG = 3% (Typ.) • Input signal ampiitude 180 IRE (= 1.28Vp-p, max.) • Low input clock amplitude operation 200mVp-p (Min.
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