ST1005SRG
Description
ST1005SRG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance.
Key Features
- -100V/-0.8.0A, RDS(ON) = 650m-ohm (Typ.) @VGS = -10V l
- -60V/-0.4A, RDS(ON) = 700m-ohm @VGS = -4.5V l
- Super high density cell design for extremely low RDS(ON) l
- Exceptional on-resistance and maximum DC current capability l
- SOT-23 package design
- Gate 2.Source 3.Drain
