Datasheet4U Logo Datasheet4U.com

STP2230SOP - Uniprocessor System Controller

This page provides the datasheet information for the STP2230SOP, a member of the STP2200ABGA Uniprocessor System Controller family.

Datasheet Summary

Description

The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the flow of requests and data on the UPA bus.

It also controls the resets going to all UPA clients.

Features

  • Controls up to eight standard SS-10/SS-20-type DRAM SIMMs.
  • Supports various memory SIMM organizations: 16 MB, 64 MB, and 256 MB as well as dual-stacked 128-MB SIMMs.
  • Controls and generates a number of resets for the system.
  • Programmed via a standard 8-bit asynchronous interface (EBus).
  • JTAG interface allows full chip scan.
  • 225-pin ABGA package Benefits.
  • Standard workstation memory.
  • Flexibility.
  • High integration.

📥 Download Datasheet

Datasheet preview – STP2230SOP

Datasheet Details

Part number STP2230SOP
Manufacturer Sun
File Size 441.25 KB
Description Uniprocessor System Controller
Datasheet download datasheet STP2230SOP Datasheet
Additional preview pages of the STP2230SOP datasheet.

📁 Similar Datasheet

  • STP220N6F7 - N-channel Power MOSFET (STMicroelectronics)
  • STP2270 - STRATUM 3E OCXO (Rakon)
  • STP22NE03L - N-CHANNEL ENHANCEMENT MODE SINGLE FEATURE SIZE POWER MOSFET (ST Microelectronics)
  • STP22NE10L - N-CHANNEL STripFET POWER MOSFET (ST Microelectronics)
  • STP22NF03L - N-Channel Power MOSFET (ST Microelectronics)
  • STP22NM50 - N-CHANNEL Power MOSFET (ST Microelectronics)
  • STP22NM50FP - N-CHANNEL Power MOSFET (ST Microelectronics)
  • STP22NM60 - N-CHANNEL Power MOSFET (ST Microelectronics)
  • STP22NM60FP - N-CHANNEL Power MOSFET (STMicroelectronics)
  • STP22NM60N - Power MOSFET (ST Microelectronics)
Other Datasheets by Sun

Full PDF Text Transcription

Click to expand full text
STP2200ABGA July 1997 USC DATA SHEET DESCRIPTION The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the flow of requests and data on the UPA bus. It also controls the resets going to all UPA clients.
Published: |