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T2316407A - (T2316405A / T2316407A) EDO/FPM DRAM

General Description

The T2316405A and T2316407A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x 4 configuration.

It offers Fast Page mode with Extended Data Output (EDO).

Key Features

  • Industry-standard x 4 pinouts and timing functions.
  • power supply : T2316405A 2.6V(±0.2V) T2316407A 3.3V(±0.3V) www. DataSheet4U. com.
  • All device pins are TTL- compatible.
  • 2048-cycle refresh in 32 ms.
  • Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN.
  • Extended data-out (EDO) PAGE MODE access cycle. 4M x 4.

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Datasheet Details

Part number T2316407A
Manufacturer Taiwan Memory Technology
File Size 173.15 KB
Description (T2316405A / T2316407A) EDO/FPM DRAM
Datasheet download datasheet T2316407A Datasheet

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T2316405A (T2316405A / T2316407A) EDO/FPM DRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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tm TE CH T2316405A Preliminary T2316407A DRAM FEATURES • Industry-standard x 4 pinouts and timing functions • power supply : T2316405A 2.6V(±0.2V) T2316407A 3.3V(±0.3V) www.DataSheet4U.com • All device pins are TTL- compatible. • 2048-cycle refresh in 32 ms. • Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. • Extended data-out (EDO) PAGE MODE access cycle. 4M x 4 DYNAMIC RAM EDO PAGE MODE GRNERAL DESCRIPTION The T2316405A and T2316407A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x 4 configuration. It offers Fast Page mode with Extended Data Output (EDO). During READ or WRITE cycles, each of the 4 memory bits (1 bit per I/O) is uniquely addressed through the 22 address bits, which are entered 11 bits (A0-A10) at a time.