T2316407A Datasheet | Taiwan Memory Technology

FEATURES - Industry-standard x 4 pinouts and timing functions - power supply : T2316405A 2.6V(±0.2V) T2316407A 3.3V(±0.3V) .. - All device pins are TTL- patible. - 2048-cycle refresh in 32 ms. - Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. - Extended data-out (EDO) PAGE MODE access cycle. 4M x 4 DYNAMIC RAM EDO PAGE MODE GRNERAL DESCRIPTION The T2316405A and T2316407A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x 4 configuration. It offers Fast Page mode with Extended Data Output (EDO). During READ or WRITE cycles, each of the 4 memory bits (1 bit per I/O) is uniquely addressed through the 22 address bits, which are entered 11 bits (A0-A10) at a time. RAS latches the first 11 bits and CAS latches the latter 11 bits. A READ or WRITE cycle is selected w ith the WE input. A logic HIGH on WE dictates READ mode while a logic LOW on WE dictates WRITE mode. During a WRITE cycle, data -in is latched by the falling edge of WE or CAS , whichever occurs last. When WE goes Low prior to CAS going LOW ( EARLY WRITE cycle), the J S output pins remain open (High-Z) until the next CAS cycle. A Late Write or Read-Modify-Write occurs. When WE falls after CAS was taken LOW (Late Write cycle). OE must be taken HIGH to disable the data-outputs prior to applying input data. The four data inputs and four data outputs are routed through four pins using mon I/O, and pin direction is controlled by WE and OE . OPTION TIMING 50ns (For T2316407A only) 60ns (For T2316407A only) 70ns (For T2316407A only) 100ns (For T2316405A only) PACKAGE 26/24-pin SOJ 26/24-pin TSOP-II MARKING -50 -60 -70 -10 PIN ARRANGEMENT (Top View) Vcc I/O1 I/O2 WE RAS NC A10 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 8 9 10 11 12 13 SOJ & TSOP-II 26 25 24 23 22 21 19 18 17 16 15 14 Vss I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 Vss Taiwan Memory Technology, Inc. reserves the right P. 1 to change products or specifications without notice. Publication Date: APR 2001 Revision:0.B tm WE...