TSPC603E Overview
Description
The PID6-603e implementation of PC603e (after named 603e) is a low-power implementation of reduced instruction set computer (RISC) microprocessors PowerPC™ family. The 603e implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
Key Features
- through JTAG boundary-scan capability
- MAIN FEATURES H 2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated) H Superscalar (3 instructions per clock peak)
- H Dual 16KB caches
- H Selectable bus clock
- H 32-bit compatibility PowerPC implementation
