TSPC603R Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power implementation of the Reduced Instruction Set puter (RISC) microprocessor PowerPC family. The 603R is pin-to-pin patible with the PowerPC 603e and 603P in a Cerquad package. The 603R implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
TSPC603R Key Features
- Superscalar (3 Instructions per Clock Peak)
- Dual 16 KB Caches
- Selectable Bus Clock
- 32-bit patibility PowerPC Implementation
- On-chip Debug Support
- Nap, Doze and Sleep Power Saving Modes
- Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255
- 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)
- PD Typically = 3.5W (266 MHz), Full Operating Conditions
- Branch Folding