TSPC603R Overview
Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power implementation of the Reduced Instruction Set Computer (RISC) microprocessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e and 603P in a Cerquad package.
Key Features
- Superscalar (3 Instructions per Clock Peak)
- Dual 16 KB Caches
- Selectable Bus Clock
- 32-bit Compatibility PowerPC Implementation
- On-chip Debug Support
- Nap, Doze and Sleep Power Saving Modes
- Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255
- PD Typically = 3.5W (266 MHz), Full Operating Conditions
- Branch Folding
- 64-bit Data Bus (32-bit Data Bus Option)
