Download the TC74AC112FN datasheet PDF.
This datasheet also covers the TC74AC112F variant, as both devices belong to the same dual j-k flip-flop family and are provided as variant models within a single manufacturer datasheet.
Key Features
High speed: fmax = 170 MHz (typ. ) at VCC = 5 V Low power dissipation: ICC = 4 µA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω
DataShee.
DataSheet4U. com transmission lines. ∼ tpHL Balanced propagation delays: tpLH.
Wide operating voltage range: VCC (opr) = 2 to 5.5 V Pin and function compatible with 74F112
Pin A.
Note: The manufacturer provides a single datasheet file (TC74AC112F_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for TC74AC112FN (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
TC74AC112FN. For precise diagrams, and layout, please refer to the original PDF.
www.DataSheet4U.com TC74AC112P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC112P,TC74AC112F,TC74AC112FN Dual J-K Flip Flop with Preset and Clear ...
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C112P,TC74AC112F,TC74AC112FN Dual J-K Flip Flop with Preset and Clear Note: The TC74AC112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. In accordance with the logic level given J and K input this device changes state on negative going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection c
TC74AC112FN Datasheet
