TC74HC592AF Overview
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The internal counter counts at positive edge of Counter Clock (CCK) when Counter Clock Enable ( CCKEN ) is held “L” level. If Counter clear ( CCLR ) is held “L”, the internal counter is cleared asynchronously to clock.
TC74HC592AF Key Features
- High speed: fmax = 35 MHz (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- High noise immunity: VNIH = VNIL = 28% VCC (min)
- Output drive capability: 10 LSTTL loads for QA to QH
- Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
- Balanced propagation delays: tpLH ∼- tpHL
- Wide operating voltage range: VCC (opr) = 2 to 6 V
- Pin and function patible with 74LS592