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TC74HC595AP - 8-Bit Shift Register/Latch

This page provides the datasheet information for the TC74HC595AP, a member of the TC74HC595AF 8-Bit Shift Register/Latch family.

Features

  • High speed: fmax = 55 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 15 LSTTL loads for QA to QH 10 LSTTL loads for QH’.
  • Symmetrical output impedance: |IOH| = IOL = 6 mA (min) For QA to QH |IOH| = IOL = 4 mA (min) For QH’.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 6 V.

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Datasheet preview – TC74HC595AP

Datasheet Details

Part number TC74HC595AP
Manufacturer Toshiba Semiconductor
File Size 273.08 KB
Description 8-Bit Shift Register/Latch
Datasheet download datasheet TC74HC595AP Datasheet
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Full PDF Text Transcription

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TC74HC595AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC595AP, TC74HC595AF 8-Bit Shift Register/Latch (3-state) The TC74HC595A is a high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The TC74HC595A contains an 8-bit static shift register which feeds an 8-bit storage register. Shift operation is accomplished on the positive going transition of the SCK input. The output register is loaded with the contents of the shift register on the positive going transition of the RCK input. Since RCK and SCK signal are independent, parallel outputs can be held stable during the shift operation.
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