Datasheet4U Logo Datasheet4U.com

TC74HC74AFN - CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear

Download the TC74HC74AFN datasheet PDF (TC74HC74AF included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for cmos digital integrated circuit silicon monolithic dual d-type flip flop preset and clear.

Features

  • High speed: fmax = 77 MHz (typ. ) at VCC = 5 V Low power dissipation: ICC = 2 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Output drive capability: 10 LSTTL loads Symmetrical output impedance: |IOH| = IOL = 4 mA (min) ∼ tpHL Balanced propagation delays: tpLH.
  • Wide operating voltage range: VCC (opr) = 2~6 V Pin and function compatible with 74LS74 TC74HC74AFN Pin Assignment Weight DI.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC74AF_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Other Datasheets by Toshiba Semiconductor

Full PDF Text Transcription

Click to expand full text
TC74HC74AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic www.DataSheet4U.com TC74HC74AP,TC74HC74AF,TC74HC74AFN Dual D-Type Flip Flop Preset and Clear The TC74HC74A is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CLOCK pulse. CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the appropriate input to an “L” level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Note: xxxFN (JEDEC SOP) is not available in Japan.
Published: |