TH50VSF2581AASB SRAM AND FLASH MEMORY MIXED MULTI-CHIP Datasheet

TH50VSF2581AASB Key Features

Data retention supply voltage VCCs = 1.5 V~3.6 V
Current consumption Operating: 45 mA maximum (CMOS level) Standby: 7 µA maximum (SRAM CMOS level) Standby: 10 µA maximum
Block erase architecture for flash memory 8 blocks of 8 Kbytes 63 blocks of 64 Kbytes
Organization
CIOF = VCC, CIOS = VCC (×16, ×16)
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devic

Part Number	Description
TH50VSF2580AASB	SRAM AND FLASH MEMORY MIXED MULTI-CHIP
TH50VSF2582AASB	SRAM AND FLASH MEMORY MIXED MULTI-CHIP
TH50VSF2583AASB	SRAM AND FLASH MEMORY MIXED MULTI-CHIP
TH50VSF3582AASB	MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS
TH50VSF3583AASB	MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS