TH50VSF2583AASB Datasheet | Toshiba

TH50VSF2582/2583AASB TENTATIVE TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE DESCRIPTION The TH50VSF2582/2583AASB is a mixed multi-chip package containing a 4,194,304-bit full CMOS SRAM and a 33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration. The power supply for the TH50VSF2582/2583AASB can range from 2.7 V to 3.6 V. The TH50VSF2582/2583AASB can perform simultaneous read/write operations on its flash memory and is available in a 69-pin BGA package, making it suitable for a variety of applications. Features Power supply voltage VCCs = 2.7 V~3.6 V V = 2.7 V~3.6 V ..CCf - Data retention supply voltage VCCs = 1.5 V~3.6 V - Current consumption Operating: 45 m A maximum (CMOS level) Standby: 7 µA maximum (SRAM CMOS level) Standby: 10 µA maximum (flash CMOS level) - Block erase architecture for flash memory 8 blocks of 8 Kbytes 63 blocks of 64 Kbytes - Organization - CIOF VCC VCC VSS CIOS VCC VSS VSS Flash Memory 2,097,152 words of 16 bits 2,097,152 words of 16 bits 4,194,304 words of 8 bits SRAM 262,144 words of 16 bits 524,288 words of 8 bits 524,288 words of 8 bits - - - - - Function mode control for flash memory patible with JEDEC-standard mands Flash memory functions Simultaneous Read/Write operations Auto-Program Auto Chip Erase, Auto Block Erase Auto Multiple-Block Erase Program Suspend/Resume Block-Erase Suspend/Resume Data Polling / Toggle Bit function Block Protection / Boot Block Protection Support for automatic sleep and hidden ROM area mon flash memory interface (CFI) Byte/Word Modes Erase and Program cycles for flash memory 105 cycles (typical) Boot block architecture for flash memory TH50VSF2582AASB: Top boot block TH50VSF2583AASB: Bottom boot block Package P-FBGA69-1209-0.80A3: 0.31 g (typ.) PIN ASSIGNMENT (TOP VIEW) - CIOF = VCC, CIOS = VCC (×16, ×16) 1 2 3 4 5 6 7 8 9 10 PIN NAMES A0~A21 A12S A12F SA...