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TC58NVG2D4BFT00 - 4 GBIT (512M X 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG2D4B is a single 3.3 V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 128 pages × 2048 blocks.

Key Features

  • Organization Memory cell array Register Page size Block size.
  • TC58NVG2D4B 2112 × 256K × 8 2112 × 8 2112 bytes (256K + 4K) bytes Modes Read, Read with Data Cache, Reset, Auto Page Program, Auto Page Program with Data Cache, Multi Page Program with Cache, Auto Block Erase, Status Read, Page Copy Mode control Serial input/output Command control Number of valid blocks Max 2048 blocks Min 1968 blocks Power supply VCC = 2.7 V to 3.6 V Program/Erase Cycles TBD Cycles (With 4bit/528B.

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Datasheet Details

Part number TC58NVG2D4BFT00
Manufacturer Toshiba
File Size 634.22 KB
Description 4 GBIT (512M X 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TC58NVG2D4BFT00 Datasheet

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Full PDF Text Transcription for TC58NVG2D4BFT00 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for TC58NVG2D4BFT00. For precise diagrams, tables, and layout, please refer to the original PDF.

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TOSHIBA CONFIDENTIAL TENTATIVE TC58NVG2D4BFT00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 4 GBIT (512M × 8 BIT) CMOS NAND E PROM (Multi Level Cell) DESCRIPTION The TC58NVG2D4B is a single 3.3 V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 128 pages × 2048 blocks. The device has two 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 8 Kbytes: 2112 bytes × 128 pages). The TC58NVG2D4B is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.