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TC58NVG5D2FTA00 - 32 GBIT (4G X 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG5D2 is a single 3.3 V 32 Gbit (36,274,176,000 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 448) bytes × 128 pages × 4100 blocks.

Key Features

  • Organization Memory cell array Register Page size Block size.
  • TC58NVG5D2F 8640 × 512K × 8 8640 × 8 8640 bytes (1M + 56 K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Mullti Page Read Mode control Serial input/output Command control Number of valid blocks Min 3936 blocks Max 4100 blocks Power supply VCC = 2.7 V to 3.6 V Access time Cell array to register Serial Read Cycle Program/.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TOSHIBA CONFIDENTIAL TENTATIVE TC58NVG5D2FTA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 32 GBIT (4G × 8 BIT) CMOS NAND E PROM (Multi-Level-Cell) DESCRIPTION The TC58NVG5D2 is a single 3.3 V 32 Gbit (36,274,176,000 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 448) bytes × 128 pages × 4100 blocks. The device has two 8640-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8640-byte increments. The Erase operation is implemented in a single block unit (1 Mbytes + 56 Kbytes: 8640 bytes × 128 pages). The TC58NVG5D2 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.