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TC74HC40105AF - 4-Bit x 16 Word FIFO Register

Download the TC74HC40105AF datasheet PDF. This datasheet also covers the TC74HC40105AP variant, as both devices belong to the same 4-bit x 16 word fifo register family and are provided as variant models within a single manufacturer datasheet.

General Description

SI pin.

DIR will toggle momentarily until the data has been transferred to the second word register.

SI must be toggled before the next 4-bit word can be written.

Key Features

  • High speed: fmax 25 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 10 LSTTL loads for DIR, DOR 15 LSTTL loads for Q0 to Q3.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) for DIR, DOR |IOH| = IOL = 6 mA (min) for Q0 to Q3.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC40105AP-Toshiba.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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TC74HC4040AP 12-Stage Binary Counter Toshiba Semiconductor

Other Datasheets by Toshiba

Part Number Description
TC74HC40105AP 4-Bit x 16 Word FIFO Register
TC74HC40102AF Dual BCD Programmable Down Counter
TC74HC40102AP Dual BCD Programmable Down Counter
TC74HC40103AF 8-Bit Binary Programmable Down Counter
TC74HC40103AP 8-Bit Binary Programmable Down Counter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HC40105AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC40105AP, TC74HC40105AF 4 Bit × 16 Word FIFO Register The TC74HC40105A is a high speed CMOS 4 bit × 16 word first-in, first-out (FIFO) Strage Register fabricated with silicon gate C2MOS technology. It achieves the high speed operation while maintaining the CMOS low power dissipation. The device is capable of handling 16 four-bit words and it is possible to handle the input and output data at different shifting rates. When the DATA-IN-READY (DIR) is high, data is written into the registers by a low to high transition of the SHIFT IN (SI) input. And when DATA-OUT-READY (DOR) is high, data is read out of the registers by a high to low transition of the SHIFT OUT ( SO ) input.