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TH58NVG2S3BTG00 - 4-Gbit CMOS NAND EPROM

General Description

The TH58NVG2S3B is a single 3.3 V 4Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 4096 blocks.

Key Features

  • Organization TH58NVG2S3B 2112 × 128K × 8 × 2 2112 × 8 2112 bytes (128K + 4K) bytes Memory cell array www. DataSheet4U. com Register Page size Block size.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read Mode control Serial input/output Command control Number of valid blocks Max 4096 blocks Min 4016 blocks Power supply VCC = 2.7 V to 3.6 V Program/Erase Cycles 100000 Cycles (With ECC) Access time Cell array to register Serial Read Cycle Program/Erase.

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Full PDF Text Transcription (Reference)

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TH58NVG2S3BTG00 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 4 GBIT (512M × 8 BIT) CMOS NAND E PROM DESCRIPTION Lead-Free The TH58NVG2S3B is a single 3.3 V 4Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 4096 blocks. The device has a 2112-byte static register which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TH58NVG2S3B is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.