TH58NVG3D4BTG00 Datasheet | Toshiba

TOSHIBA CONFIDENTIAL TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 8 GBIT (1024M × 8 BIT) CMOS NAND E2PROM (Multi Level Cell) Lead-Free DESCRIPTION The TH58NVG3D4B is a single 3.3 V 8 Gbit (8,858,370,048 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 128 pages × 4096blocks. The device has a 2112-byte static register which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 8 Kbytes: 2112 bytes × 128 pages). The TH58NVG3D4B is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for mand inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. Features - Organization Memory cell array Register Page size Block size TH58NVG3D4B 2112 × 256K × 8 × 2 2112 × 8 2112 bytes (256K + 8K) bytes - Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read - Mode control Serial input/output mand control - Number of valid blocks Max 4096 blocks Min 3936 blocks - Power supply VCC = 2.7 V to 3.6 V - Program/Erase Cycles 10000 Cycles (With 4bit/528Byte ECC) - Access time Cell array to register 50 µs max Serial Read Cycle 50 ns min - Program/Erase time Auto Page Program Auto Block Erase 800 µs/page typ. 3 ms/block typ. - Operating current Read (50 ns cycle) Program (avg.) Erase (avg.) Standby 10 m A typ. 10 m A typ. 10 m A typ. 100 µA max - Package TH58NVG3D4BTG00 TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.) -...