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TH58NVG3D4BTG00 - 8 GBIT (1024M x 8 BIT) CMOS NAND E2PROM

Datasheet Summary

Description

Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 128 pages × 4096blocks.

Features

  • Organization Memory cell array Register Page size Block size TH58NVG3D4B 2112 × 256K × 8 × 2 2112 × 8 2112 bytes (256K + 8K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Max 4096 blocks Min 3936 blocks.
  • Power supply VCC = 2.7 V to 3.6 V.
  • Program/Erase Cycles 10000 Cycles (With 4bit/528Byte ECC).
  • Access time Cell array to r.

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Datasheet Details

Part number TH58NVG3D4BTG00
Manufacturer Toshiba
File Size 306.07 KB
Description 8 GBIT (1024M x 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TH58NVG3D4BTG00 Datasheet
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Full PDF Text Transcription

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TOSHIBA CONFIDENTIAL TH58NVG3D4BTG00 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 8 GBIT (1024M × 8 BIT) CMOS NAND E2PROM (Multi Level Cell) Lead-Free DESCRIPTION The TH58NVG3D4B is a single 3.3 V 8 Gbit (8,858,370,048 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 128 pages × 4096blocks. The device has a 2112-byte static register which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 8 Kbytes: 2112 bytes × 128 pages).
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