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TH58TEG7DCJTAK0 - NAND memory Toggle DDR1.0

Download the TH58TEG7DCJTAK0 datasheet PDF. This datasheet also covers the TC58TEG variant, as both devices belong to the same nand memory toggle ddr1.0 family and are provided as variant models within a single manufacturer datasheet.

Description

Toggle DDR is a NAND interface for high performance applications which support data read and write operations using bidirectional DQS.

Toggle DDR NAND has implemented ’Double Data Rate’ without a clock.

Features

  • Organization Table 1 Product Organization Parameter Part number (TOPER: 0~70℃) Part number (TOPER: -40~85℃) Device capacity Page size Block size Plane size Plane per one LUN LUN per one target Target per one device Number of valid blocks per a device (min) Number of valid blocks per a device (max) TC58TEG6DCJ TC58TEG6DCJTA00 TC58TEG6DCJTAI0 17664×256×2092×8 bits 17664 Bytes (4M + 320 K) Bytes 9459990528Bytes 1 Planes 1 LUNs 1 target 2018 2092 TH58TEG7DCJ TH58TEG7DCJTA20 TH58TEG7DCJTAK0 17664×.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC58TEG-6DCJTA00.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription

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TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 TOSHIBA NAND memory Toggle DDR1.0 Technical Data Sheet Rev. 0.3 2012 – 04 – 10 TOSHIBA Semiconductor & Storage Products Memory Division TC58TEG6DCJTA00 / TC58TEG6DCJTAI0 TH58TEG7DCJTA20 / TH58TEG7DCJTAK0 TH58TEG8DCJTA20 / TH58TEG8DCJTAK0 0 TENTATIVE 2012-04-10C 1. INTRODUCTION TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0 1.1. General Description Toggle DDR is a NAND interface for high performance applications which support data read and write operations using bidirectional DQS. Toggle DDR NAND has implemented ’Double Data Rate’ without a clock. It is compatible with functions and command which have been supported in conventional type NAND(i.e.
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