TQ8101C Datasheet | TriQuint Semiconductor

Features - Byte-wide Multiplexing, Demultiplexing, Framing, and PLL (MDFP) in one device - Choice of STS-12/STM-4 or STS-3/STM-1 transmission rates - Configurable master or slave reference clock generation and PLL bypass for external clocking - 77.76 MHz or 19.44 MHz output for the multiplexer; 77.76 MHz or 19.44 MHz and 51.84 MHz output for the demultiplexer - External RC loop filter - Pass-through mode and three loopback modes for enhanced filed diagnostics - Frame-synchronous and bytealigned demultiplexer output, pliant with SONET and SDH - Search, detect, and recovery of framing on out-of-frame input - Standard TTL and differential or single-ended ECL I/O (except TXCK) - Tristate TTL output for factory circuit-board testability - 68-pin Tri Quint MLC controlled-Z surface-mount package with integral heat spreader - - - - - - Transmission system transport cards Switch and cross-connect line cards Repeaters ATM physical layer interfaces Test equipment Add/drop multiplexers Figure 1. Logical Application TQ8101C MDFP MXDT(7:0) DXDT(7:0) OOF MXCK0 DXSYNC DXCK O/E Rx + TQ8103 CDR OC-3 or OC-12 Driver and LASER OC-3 or OC-12 600 Ω 0.68 µF VEE PM5312 or PM5355 STTX S/UNI-622 TOUT(7:0) RIN(7:0) OHFP OOF TCLK RIFP RICLK CNTL(3:0) 8-bit data 8-bit data OOF fix- 51.84 MHz CMOS OSC - Contact PMC-Sierra for application note. - Dual-supply operation (+5V, - 5.2V) - Low power dissipation (2.3W nom.) For additional information and latest specifications, see our website: .triquint. Figure 2. TQ8101C Block Diagram MXDT(7:0) Mux TXDT TXCK CNTL(3:0) MO Control Block Serial-to-Parallel Converter Loopback Block 2 2 RXDT RXCK TUNE IOUT MXCK(2:0) PLL Clock Synthesizer Mux...