TQ8016 Description
Differential Data Inputs Differential Data Inputs Differential Data Inputs Differential Data Outputs Differential Data Outputs Input Address Output Address Switch Reconfiguration 3 For additional information and latest specifications, see our website:.
TQ8016 Key Features
- >1.3 Gigabit/sec data rate
- Non-blocking architecture
- +200 ps delay match (one input to all outputs)
- ECL-level data inputs/outputs; CMOS-level control inputs
- Low crosstalk
- Fully differential data path
- Double row of output select latches minimizes reconfiguration time
- Available in 132-pin leaded chip carrier
- DATA IN 0 (I0)
- DATA OUT 15 (O15) DATA OUT 0 (O0)