TQ8033 Description
Data Inputs The 64 data input channels are differential PECL patible. All inputs have a 2.5KΩ Thevenin equivalent bias circuit which holds the DC bias at VDD-1.3 Volts simplifying the design of applications requiring AC coupling. Input signals must be properly terminated for maximum performance.
TQ8033 Key Features
- >1.5 Gb/s/port data rate >50 Gb/s aggregate bandwidth
- Differential PECL data path with 64 inputs and 33 outputs
- Non-blocking architecture supports Broadcast and Multicast operation
- Data inputs internally biased for AC coupling
- Low jitter and signal skew
- Double-buffered configuration latches
- TTL configuration control inputs