TQ8032 Description
Differential data input ports. Differential data output ports. Input port selection address that is written into the selected output port program latches (OA0:4).
TQ8032 Key Features
- >25 Gb/s aggregate BW
- 800 Mb/s/port NRZ data rate
- Non-blocking architecture
- 500 ps delay match
- Differential ECL-level data I/O; Selectable CMOS/TTLlevel control inputs
- Low jitter and signal skew
- Fully differential data path
- Double buffered configuration latches
- 196-pin CQFP package