SI6966EDQ Datasheet | Vishay

DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. .. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a mercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70074 22-Oct-04 .vishay. SPICE Device Model Si6966EDQ Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Schottky Diode Forward Voltagea VGS(th) ID(on) r DS(on) gfs VSD VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 4.5 V VGS = 4.5 V, ID = 5.2 A VGS = 2.5 V, ID = 4.5 A VDS = 10 V, ID = 5.2 A IS = 1.25 A, VGS = 0 V IS = 1.25 A, VGS = 0 V, Tj = 125°C 0.923 120 0.02 0.027 19.5 0.65 0.57 V A Ω S V Symbol Test Conditions Typical Unit Dynamicb Total Gate Chargeb Gate-Source Charge b Qg Qgs Qgd td(on) tr td(off) tf trr IF = 1.25 A, di/dt = 100 A/µs VDD = 10 V, RL = 10 Ω ID ≅ 1 A, VGEN = 4.5 V, RG = 6 Ω VDS = 15 V, VGS = 4.5 V, ID = 5.2 A 13.4 2.1 5.7 0.35 76 131 290 210 ns n C .. Gate-Drain Charge Rise Timeb b Turn-On Delay Timeb Turn-Off Delay Timeb Fall Timeb Source-Drain Reverse Recovery Time Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production...