Si5442DU Datasheet | Vishay

FEATURES PRODUCT SUMMARY VDS (V) RDS(on) () Max. 0.0100 at VGS = 4.5 V 20 0.0115 at VGS = 2.5 V 0.0135 at VGS = 1.8 V ID (A)a 25 25 25 16.6 n C Qg (Typ.) Power PAK Chip FET Single 1 2 D D D D D D G S S - Trench FET® Power MOSFET - Thermally Enhanced Power PAK® Chip FET® Package - Small Footprint Area - Low On-Resistance - Thin 0.8 mm Profile - 100% Rg Tested - Material categorization: For definitions of pliance please see .vishay./doc?99912 APPLICATIONS 3 4 8 7 - - - - Load Switch, PA Switch, and for Portable Applications Point-of-Load DC/DC Converters Power Management D Marking Code AQ XXX Lot Traceability and Date Code 6 5 1.9 mm Bottom View Part # Code Ordering Information: Si5442DU-T1-GE3 (Lead (Pb)-free and Halogen-free) S N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Symbol VDS VGS ID IDM IS Limit 20 ±8 25a 25a 12.4b, c 9.9b, c 60 25a 2.6b, c 31 20 3.1b, c 2b, c - 55 to 150 260 Unit V Continuous Drain Current (TJ = 150 °C) Pulsed Drain Current (t = 300 µs) TC = 25 °C TA = 25 °C TC = 25 °C TC = 70 °C Maximum Power Dissipation TA = 25 °C TA = 70 °C Operating Junction and Storage Temperature Range Continuous Source-Drain Diode Current Soldering Remendations (Peak Temperature)d, e PD TJ, Tstg °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambientb, f Maximum Junction-to-Case (Drain) t5s Steady State Symbol Rth JA Rth JC Typical 34 3 Maximum 40 4 Unit °C/W Notes: a. Package limited. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. See solder profile (.vishay./doc?73257). The Power PAK Chip FET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual...