Description
FD0-15 SD0-15 A0-18 Flash Data Inputs/Outputs SRAM Data Inputs/Outputs Address Inputs SRAM Write Enable SRAM Chip Selects Output Enable Power Supply Ground Not Connected Flash Write Enable Flash Chip Select
56
SWE1-2# SCS1-2# OE# VCC GND NC FWE1-2# FCS1-2#
Block Diagram
S W E 1 # S CS 1 # S W E 2
Features
- Access Times of 35ns (SRAM) and 90ns (FLASH) Access Times of 70ns (SRAM) and 120ns (FLASH) Packaging.
- 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic HIP (Package 402).
- 68 lead, Hermetic CQFP (G2), 22mm (0.880") square (Package 500). Designed to fit JEDEC 68 lead 0.990” CQFJ footprint (FIGURE 2) 512Kx16 SRAM 512Kx16 5V FLASH Organized as 512Kx16 of SRAM and 512Kx16 of Flash Memory with separate Data Busses Both blocks of memory are User Configurable as 1Mx8 Low Power CMOS C.
WSF512K16-XXX Datasheet
