GENERAL DESCRIPTION
1M × 4 BANKS × 16 BITS SDRAM Using pipelined architecture and 0.175 µm process technology, W986416DH delivers a data bandwidth of up to 366M bytes per second (-55). The -55 parts can run up to 183 MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For handheld device application, we also provide a low power option, the grade of –7L, with Self Refresh Current under 400 µA and work well at 2.7V during Self Refresh Mode. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance.
Winbond Electronics Corporation
