XC9536 Datasheet | Xilinx

Features - - - - - 5 ns pin-to-pin logic delays on all pins f CNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full mercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 m A outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V Fast FLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages Power Management Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (m A) = MCHP (1.7) + MCLP (0.9) + MC (0.006 m A/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9536 device. - - - - - - - - - - - - erform High P ance (83) Typical ICC (m A) (50) (50) ower Low P (30) Description The XC9536 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is prised of two 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for the architecture overview . 0 50 Clock Frequency (MHz) 100 X5920 Figure 1: Typical ICC vs....