XC9536 Datasheet PDF - Xilinx XC9536 In-System Programmable CPLD Specs

XC9536 - XC9536 In-System Programmable CPLD

Datasheet Summary

Description

The XC9536 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration.

It is comprised of two 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns.

See Figure 2 for the architecture overview.

Features

5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, se.

Datasheet Details

Part number	XC9536
Manufacturer	Xilinx
File Size	61.42 KB
Description	XC9536 In-System Programmable CPLD
Datasheet	XC9536 Datasheet
Additional preview pages of the XC9536 datasheet.

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Full PDF Text Transcription

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9 1 ® XC9536 In-System Programmable CPLD 1 1* December 4, 1998 (Version 5.0) Product Specification Features • • • • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.

Published: Apr 16, 2005 |