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XC9536XL - High Performance CPLD

Datasheet Summary

Features

  • 5 ns pin-to-pin logic delays.
  • System frequency up to 178 MHz.
  • 36 macrocells with 800 usable gates.
  • Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins) - 64-pin VQFP (36 user I/O pins) - Pb-free available for all packages.
  • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals - 3.3V or 2.5V output ca.

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Datasheet preview – XC9536XL

Datasheet Details

Part number XC9536XL
Manufacturer Xilinx
File Size 182.68 KB
Description High Performance CPLD
Datasheet download datasheet XC9536XL Datasheet
Additional preview pages of the XC9536XL datasheet.

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Full PDF Text Transcription

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0 R XC9536XL High Performance CPLD DS058 (v1.9) April 3, 2007 00 Features • 5 ns pin-to-pin logic delays • System frequency up to 178 MHz • 36 macrocells with 800 usable gates • Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins) - 64-pin VQFP (36 user I/O pins) - Pb-free available for all packages • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.
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