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ZL30120 - SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer

Description

11 1.1 DPLL

Features

  • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-1244-CORE, GR-253CORE, ITU-T G.813, and compatible with ITU-T G.8261 (formerly G. pactiming) Internal low jitter APLL provides SONET/SDH clocks including 6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz, or 25 MHz and 50 MHz Synchronous Ethernet output clocks Programmable output synthesizers (P0, P1) generate general p.

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Datasheet Details

Part number ZL30120
Manufacturer Zarlink Semiconductor
File Size 349.94 KB
Description SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
Datasheet download datasheet ZL30120 Datasheet
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Full PDF Text Transcription

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www.DataSheet4U.com ZL30120 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30120GGG 100 Pin CABGA Trays ZL30120GGG2 100 Pin CABGA** Trays **Pb Free Tin/Silver/Copper -40oC to +85oC • Provides two DPLLs which have independent modes of operation (locked, free-run, holdover) and optional hitless reference switching.
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