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ZL30123 - Low Jitter Line Card Synchronizer

Description

11 1.1 DPLL

Features

  • for generating derived output clocks and other general purpose clocks Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 sync inputs for output frame pulse alignment Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Configurable input to output delay, and output to output phase alignment Flexible input reference monitoring automatically disqualifies references b.

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Datasheet Details

Part number ZL30123
Manufacturer Zarlink Semiconductor
File Size 353.69 KB
Description Low Jitter Line Card Synchronizer
Datasheet download datasheet ZL30123 Datasheet
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Full PDF Text Transcription

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www.DataSheet4U.com ZL30123 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30123GGG 100 Pin CABGA Trays ZL30123GGG2 100 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC • DPLL2 provides a comprehensive set of features for generating derived output clocks and other general purpose clocks Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.
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