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A3V56S40GTP - 256M Single Data Rate Synchronous DRAM

This page provides the datasheet information for the A3V56S40GTP, a member of the A3V56S30GTP 256M Single Data Rate Synchronous DRAM family.

Datasheet Summary

Description

A3V56S30GTP is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and A3V56S40GTP is organized as 4-bank x 4,194,304-word x 16-bit.

All inputs and outputs are referenced to the rising edge of CLK.

Features

  • - Single 3.3V ±0.3V power supply - Maximum clock frequency: -60:166MHz/-70:143MHz/-75:133MHz - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0, BA1 (Bank Address) - CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- DQM (A3V56S30GTP), LDQM and UDQM (A3V56S40GTP) - Random column access - Auto precharge / All bank precharge contro.

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Datasheet Details

Part number A3V56S40GTP
Manufacturer Zentel
File Size 0.99 MB
Description 256M Single Data Rate Synchronous DRAM
Datasheet download datasheet A3V56S40GTP Datasheet
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A3V56S30GTP A3V56S40GTP 256M Single Data Rate Synchronous DRAM 256Mb Synchronous DRAM Specification A3V56S30GTP A3V56S40GTP Industrial Version Zentel Electronics Corp. I Revision 1.0 Jun., 2013 A3V56S30GTP A3V56S40GTP 256M Single Data Rate Synchronous DRAM General Description A3V56S30GTP is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and A3V56S40GTP is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. A3V56S30GTP and A3V56S40GTP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems. Features - Single 3.3V ±0.
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