EZ80F91
Overview
- Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core (referred as The CPU in this document)
- 10/100 BaseT ethernet media access controller with Media-Independent Interface (MII)
- 256 KB Flash memory
- 16 KB SRAM (8 KB user and 8 KB Ethernet)
- Low-power features including SLEEP mode, HALT mode, and selective peripheral power-down control
- Two Universal Asynchronous Receiver/Transmitter (UART) with independent Baud Rate Generators (BRG)
- Serial Peripheral Interface (SPI) with independent clock rate generator
- I2C with independent clock rate generator
- IrDA-compliant infrared encoder/decoder
- Glueless external peripheral interface with 4 Chip Selects, individual Wait State generators, an external WAIT input pin-supports Z80-, Intel-, and Motorola-style buses
