EV12DS130A Datasheet | e2v

Low Power 12-bit 3 Gsps DAC with 4/2:1 MUX - Preliminary MAIN Features - 12-bit resolution - 3 Gsps guaranteed Conversion rate - 4:1 or 2:1 integrated parallel MUX (selectable) - Low latency time 3.5 clock cycle. - 1.2 Watt Power Dissipation - Functions - Selectable MUX ratio 4:1 (full speed), 2:1 (half speed) - User-friendly functions: o Return to Zero, Non Return to Zero, RF modes o Gain Adjustment o Diode for die junction temperature monitoring o Setup time and Hod time violation flags (STVF, HTVF) o Clock phase shift select for synchronization with DSP (PSS[2:0]) o Output clock division selection (possibility to change the division ratio of the DSP clock) o Input data check bit (IDC_P, IDC_N) for timing with FPGA check - LVDS differential data input and DSP clock output - Analog output swing: 1Vpp differential (100Ω differential impedance) - Power up reset - External asynchronous reset for synchronization of multiple Mux DACs - Power supplies : 3.3 V (Digital), 3.3V & 5V (Analogue) - fp BGA 196 Package (15 x 15 mm body size, 1 mm pitch) - Evaluation board with state of the art FPGA for full speed testing PERFORMANCES - Broadband o NPR (-12 d BFS peak to RMS loading factor): 52 d B at Fs = 3 Gsps: 10 Bit equivalent (20 MHz to 900 MHz Broadband pattern, 25 MHz notch centered around 450 MHz) - Single tone o SFDR in Baseband (NRZ): 62 d Bc(-70 d Bm highest spur level) at Fs = 3 Gsps over Full Nyquist zone (Full Scale output) 66 d Bc (-70 d Bm highest spur level) at Fs = 3 Gsps over Full Nyquist zone (-3 d BFS output) o SFDR in 2nd Nyquist Zone (RTZ) 66 d Bc (-77 d Bm highest spur level) at Fs = 3 Gsps over Full Nyquist zone (Full Scale output) 63 d Bc (-77 d Bm highest spur level) at Fs = 3 Gsps over Full Nyquist zone (-3 d BFS output). o SFDR in 2nd and 3rd Nyquist Zones (RF) 66d Bc (-76 d Bm highest spur level) at Fs = 3Gsps over Full second and third Nyquist Zones (Full Scale output) 63d Bc (-76 d Bm highest spur level) at Fs=3Gsps over Full second and...